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High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
DESCRIPTION
The CS18LV10245 is a high performance, high speed and super low power CMOS Static Random Access Memory organized as 131,072 words by 8bits and operates from a wide range of 4.5 to 5.5V supply voltage. Advanced CMOS technology and circuit techniques provide both high speed, super low power features and maximum access time of 55/70ns in 5V operation. Easy memory expansion is provided by an active LOW chip enable (/CE) and active LOW output enable (/OE). The CS18LV10245 has an automatic power down feature, reducing the power consumption significantly when chip is deselected. The CS18LV10245 is available in JEDEC standard 32-pin sTSOP - I (8x13.4 mm), TSOP - I (8x20mm), SOP (450 mil) and PDIP (600 mil) packages.
FEATURES
1. 2. 3. Fully static operation and Tri-state output TTL compatible inputs and outputs Ultra low power consumption : 2.0V (min) data retention Low operation voltage : 4.5 ~ 5.5V ; 5mA1MHz (Max.) operating current (Vcc = 5.0V) 4. 5. Standby Typ. = 0.50uA, (Typical value @ Vcc = 5.0V, TA = 25 0C)
Standard pin configuration 32 - SOP 450mil 32 - sTSOP-I - 8X13.4mm 32 - TSOP-I 8X20mm
32 - PDIP 600mil
Product Family
Part No. CS18LV10245CC CS18LV10245DC CS18LV10245EC CS18LV10245LC CS18LV10245CI CS18LV10245DI CS18LV10245EI CS18LV10245LI Note: Green package part no, sees order information. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P1 -40~85oC 0~70oC 0.50uA Operating Temp Vcc. Range Speed (ns) Standby (Typ.) Package Type 32 SOP 32 STSOP 32 TSOP (I) 4.5 ~ 5.5 55/70 0.80uA 32 PDIP 32 SOP 32 STSOP 32 TSOP (I) 32 PDIP
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
PIN CONFIGURATIONS
32 SOP 450 mil 32 PDIP 600 mil
32 STSOP 8x13.4mm 32 TSOP(I) 8x20mm
BLOCK DIAGRAM
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P2
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Function
PIN DESCRIPTIONS
Name A0-A16 Address Input /CE Chip Enable Input CE2 Chip Enable 2 Input /WE Write Enable Input
These 17 address inputs select one of the 131,072 x 8-bit words in the RAM.
/CE is active LOW and CE2 is active HIGH. Both chip enables must be active when data read from or write to the device. If either chip enable is not active, the device is deselected and is in a standby power mode. The DQ pins will be in the high impedance state when the device is deselected.
The write enable input is active LOW and controls read and write operations. With the chip selected, when /WE is HIGH and /OE is LOW, output data will be present on the DQ pins; when /WE is LOW, the data present on the DQ pins will be written into the selected memory location.
/OE Output Enable Input
The output enable input is active LOW. If the output enable is active while the chip is selected and the write enable is inactive, data will be present on the DQ pins and they will be enabled. The DQ pins will be in the high impedance state when /OE is inactive.
DQ0-DQ7 Data Input/Output Ports Vcc Gnd
These 8 bi-directional ports are used to read data from or write data into the RAM.
Power Supply Ground
TRUTH TABLE
MODE Not Selected Output Disabled Read Write /WE X X H H L /CE H X L L L CE2 X L H H H /OE X X H L X DQ0~7 High Z High Z DOUT DIN Vcc Current ICCSB, ICCSB1 ICC ICC ICC
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P3
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
Rating
-0.5 to Vcc+0.5 -40 to +125 -60 to +150 1.0 20
ABSOLUTE MAXIMUM RATINGS (1)
Symbol VTERM TBIAS TSTG PT IOUT Parameter
Terminal Voltage with Respect to GND Temperature Under Bias Storage Temperature Power Dissipation DC Output Current
Unit
V
O O
C C
W mA
Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
OPERATING RANGE
Range Commercial Industrial Ambient Temperature
0~70 C -40~85 C
o o
Vcc
4.5V ~5.5V 4.5V ~ 5.5V
CAPACITANCE (1) (TA = 25oC, f =1.0 MHz)
Symbol CIN CDQ Parameter
Input Capacitance Input/Output Capacitance
Conditions
VIN=0V VI/O=0V
MAX. 6 8
Unit pF pF
1. This parameter is guaranteed and not tested.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P4
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
( TA = 0 to + 70 C )
o
DC ELECTRICAL CHARACTERISTICS
Parameter Name VIL VIH IIL IOL VOL VOH ICC ICCSB ICCSB1 Parameter
Guaranteed Input Low Voltage
(2)
Test Conduction
MIN
-0.5
TYP(1) MAX
0.8
Unit
V
Guaranteed Input High Voltage
(2)
2.0
Vcc+0.2
V
Input Leakage Current VCC=MAX, VIN=0 to VCC Output Leakage Current Output Low Voltage VCC=MAX, /CE=VIN, or /OE=VIN , VIO=0V to VCC VCC=MAX, IOL = 2mA VCC=MIN, IOH = -1mA /CE=VIL, IDQ=0mA, F=FMAX /CE=VIH, IDQ=0mA, /CEVCC-0.2V, VIN VCC-0.2V or VIN0.2V
o (3)
1 1
uA uA
0.4
V
Output High Voltage Operating Power Supply Current Standby Supply - TTL Standby Current -CMOS
2.4 35
V mA
2 0.3 10
mA uA
1. Typical characteristics are at TA = 25 C. 2. These are absolute values with respect to device ground and all overshoots due to system or tester notice are included.
3. Fmax = 1/tRC.
DATA RETENTION CHARACTERISTICS ( TA = 0 to +70oC )
Parameter Name VRD ICCDR TCDR tR Parameter
VCC for Data Retention Data Retention Current
Test Conduction
/CEVCC-0.2V, VINVCC-0.2V or VIN0.2V /CEVCC-0.2V, VINVCC-0.2V or VIN0.2V
MIN
1.5
TYP(1) MAX Unit
V
0.2
2.0
uA
Chip Deselect to Data Retention Time Operation Recovery Time
o
See Retention Waveform
0 tRC (2)
ns ns
1. Vcc = 3.0V, TA = + 25 C. 2. tRC= Read Cycle Time. Copyright 2004 March Chiplus Semiconductor Corp. All rights reserved. . Rev. 1.2 P5
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
LOW Vcc DATA RETENTION WAVEFORM(1) ( /CE Controlled )
LOW Vcc DATA RETENTION WAVEFORM(2) ( CE2 Controlled )
KEY TO SWITCHING WAVEFORMS
WAFEFORM INPUTS
Must be standby May change for H to L May change for L to H Don't care any change permitted Does not apply
OUTPUTS
Must be standby Will be change from H to L May change for L to H Change state unknown Center line is high impedance "OFF" state
AC TEST CONDITIONS
Input Pulse Levels Input Rise and Fall Times Input and Output Timing Reference Level 0.5Vcc Vcc/0V 5ns
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P6
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
AC ELECTRICAL CHARACTERISTICS ( TA = 0 to + 70oC , Vcc = 5.0V ) < READ CYCLE >
JEDEC Parameter Parameter Name Name tAVAX tAVQV tELQV tELQV tGLQV tE1LQX tE2LOX tGLQX tEHQZ tEHQZ tGHQZ tAXOX tRC tAA tACS1 tACS2 tOE tCLZ1 tCLZ2 tOLZ tCHZ1 tCHZ2 tOHZ tOH Description -55 -70 MAX
ns 70 70 70 30 10 10 5 25 25 25 0 0 0 10 30 30 30 ns ns ns ns ns ns ns ns ns ns ns
Unit
MIN MAX MIN
Read Cycle Time Address Access Time Chip Select Access Time (/CE) Chip Select Access Time (CE2) Output Enable to Output Valid Chip Select to Output Low Z (/CE) Chip Select to Output Low Z (CE2) Output Enable to Output in Low Z Chip Deselect to Output in High Z (/CE) Chip Deselect to Output in High Z (CE2) Output Disable to Output in High Z Out Disable to Address Change 10 10 5 0 0 0 10 55 55 55 55 20 70
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P7
High Speed Super Low Power SRAM
128K-Word By 8 Bit
NOTES: 1. /WE is high in read Cycle. 2. Device is continuously selected when /CE = VIL. 3. Address valid prior to or coincident with CE transition low.
CS18LV10245
4. /OE = VIL. 5. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is
guaranteed but not 100% tested.
SWITCHING WAVEFORMS (READ CYCLE)
READ CYCLE (1,2,4)
READ CYCLE (1,3,4)
READ CYCLE (1,4) Rev. 1.2 P8
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
AC ELECTRICAL CHARACTERISTICS ( TA = 0~70oC , Vcc = 5.0V ) < WRITE CYCLE >
JEDEC Parameter Parameter Name Name tAVAX tE1LWH tAVWL tAVWH tWLWH tWHAX tE2LAX tWLQZ tDVWH tWHDX tWHOX tWC tCW tAS tAW tWP tWR tWR2 tWHZ tDW tDH tOW Description -55 -70 MAX
ns ns ns ns ns ns ns 25 ns ns ns ns
Unit
MIN MAX MIN
Write Cycle Time Chip Select to End of Write Address Setup Time Address Valid to End of Write Write Pulse Width Write Recovery Time (/CE, /WE) Write Recovery Time (CE2, ) Write to Output in High Z Data to Write Time Overlap Data Hold from Write Time End of Write to Output Active 55 55 0 55 55 0 0 0 25 0 5 20 70 70 0 70 70 0 0 0 25 0 5
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P9
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
SWITCHING WAVEFORMS (WRITE CYCLE)
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P 10
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
NOTES: 1. TAS is measured from the address valid to the beginning of write. 2. The internal write time of the memory is defined by the overlap of /CE and /WE low. All signals must be active to initiate a write and any one signal can terminate a write by going inactive. The data input setup and hold timing should be referenced to the second transition edge of the signal that terminates the write. 3. TWR is measured from the earlier of /CE or /WE going high or CE2 going low at the end of write cycle. 4. During this period, DQ pins are in the output state so that the input signals of opposite phase to the outputs must not be applied. 5. If the /CE low transition occurs simultaneously with the /WE low transitions or after the /WE transition, output remain in a high impedance state.
Rev. 1.2 P 11
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit 6. 7. 8. 9.
CS18LV10245
/OE is continuously low (/OE = VIL ). DOUT is the same phase of write data of this write cycle. DOUT is the read data of next address. If /CE is low during this period, DQ pins are in the output state. Then the data input signals of opposite phase to the outputs must not be applied to them. 10. Transition is measured 500mV from steady state with CL = 5pF as shown in Figure 1B. The parameter is guaranteed but not 100% tested. 11. TCW is measured from the later of /CE going low to the end of write.
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P 12
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
ORDER INFORMATION
1. NON-GREEN PACKAGE:
CS18LV10245 X X - XX
Package: C: 32SOP (450mil) D: 32STSOP I (8x13.4mm) E: 32TSOP I (8x20mm) L: 32PDIP (600mil)
2. GREEN PACKAGE:
Speed: 55: 55NS 70: 70ns Grade: C: 0~70C I: -40~85C
CS18LV10245 X X X XX
Package: C: 32SOP (450mil) D: 32STSOP I (8x13.4mm) E: 32TSOP I (8x20mm) Grade: C: 0~70C I: -40~85C Speed: 55: 55ns 70: 70ns
Green Code A: Pb Free + Halogen Free (SOP / TSOP Types)
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P 13
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
PACKAGE DIMENSIONS
32 pin SOP (450 mil) :
WITH PLATING c c1 BASE METAL
b
b1
SECTION A-A
SYMBOL UNIT Min. mm A A1 A2 b 0.35 _ 0.50 b1 0.35 _ 0.46 2.645 0.102 2.540 y _ _ 0.1 _ _ 0 _ 10 0 _ 10
c 0.15 _ 0.32
c1
D
E
E1
e
L
L1
Nom. 2.821 0.229 2.680 Max. 2.997 0.356 2.820 Min.
0.15 20.320 11.176 13.792 1.118 _ 20.447 11.303 14.097 1.270
0.584 1.194 0.834 1.397 0.023 0.047 0.033 0.055 0.043
0.28 20.574 11.430 14.402 1.422 1.084 1.600
inch Nom. 0.111 0.009 0.1055
0.104 0.004 0.1000 0.014 0.014 0.006 0.006 0.800 0.440 0.543 0.044 _ _ _ _ 0.805 0.445 0.555 0.050 0.018 0.012 0.011 0.810 0.450 0.567 0.056
Max. 0.118 0.014 0.1110 0.020
0.063 0.004
-
32 pin STSOP I ( 8x13.4 mm) :
12(2x) 12(2x)
cL
1 32
E b
e
HD
Seating Plane
16 17 12(2X)
y
"A"
D
GAUGE PLANE
A A2
A 0
A1 0.254
16
17
SEATING PLANE
12(2X) L1
A L
"A" DATAIL VIEW b
WITH PLATING
c c1
1 32 BASE METAL
b1 SECTION A-A
SYMBOL UNIT Min. mm Max. inch
A 1.00 1.20
A1 0.05 0.10 0.15
A2 0.95 1.00 1.05 0.037 0.039 0.041
b 0.17 0.22 0.27 0.007 0.009
b1 0.17 0.20 0.23 0.007 0.008
c 0.10 _ 0.21 0.004 _
c1 0.10 _ 0.16 0.004 _
D 11.70 11.80 11.90 0.461 0.465 0.469
E 7.90 8.00 8.10
e 0.40 0.50 0.60
HD 13.20 13.40 13.60
L 0.40 0.50 0.70
L1 0.70 0.80 0.90
y _ _ 0.1 _ _ 0 _ 8 0 _ 8
Nom. 1.10
Min. 0.0393 0.002 Nom. 0.0433 0.004 Max. 0.0473 0.006
0.311 0.016 0.315 0.020 0.319 0.024
0.520 0.0157 0.0275 0.528 0.0197 0.0315
0.011 0.009
0.008 0.006
0.536 0.0277 0.0355 0.004
Rev. 1.2 P 14
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
High Speed Super Low Power SRAM
128K-Word By 8 Bit
CS18LV10245
-
32 pin TSOP(I) ( 8x20mm)
HD
C L
12(2X)
b
Seating Plane
16 17 12(2x)
E
1
32
e
12(2X)
y
"A"
A2
D
A
GAUGE PLANE A
0.254
0
A1
SEATING PLANE 12(2x)
A L L1
"A" DETAIL VIEW
16 17
WITH PLATING
b
c c1
1 32 BASE METAL
b1 SECTION A-A
SYMBOL UNIT Min. mm Max. inch
A 1.00 1.20
A1 0.05 0.10 0.15
A2 0.95 1.00 1.05 0.039 0.041
b 0.17 0.22 0.27 0.009
b1 0.17 0.20 0.23 0.007 0.008
c 0.10 _ 0.21 0.004 _
c1 0.10 _ 0.16 0.004 _
D 18.30 18.40 18.50 0.720 0.724 0.728
E 7.90 8.00 8.10
e 0.40 0.50 0.60
HD 19.80 20.00 20.20
L 0.40 0.50 0.70
L1 0.70 0.80 0.90
y _ _ 0.1 _ _ 0 _ 8 0 _ 8
Nom. 1.10
Min. 0.0393 0.002 Nom. 0.0433 0.004 Max. 0.0473 0.006
0.037 0.007
0.311 0.016 0.315 0.020 0.319 0.024
0.779 0.0157 0.0275 0.787 0.0197 0.0315
0.011 0.009
0.008 0.006
0.795 0.0277 0.0355 0.004
-
32 pin PDIP ( 600 mil)
SYMBOL UNIT Min. mm Nom. Max. Min. inch
A1 0.254 _ _
A2
B
B1
c
D
E
E1
e
eB
L
S
Q1
3.785 0.330 1.143 3.912 0.457 1.270 4.039 0.584 1.397 0.018 0.050
16.002 3.048 1.651 1.651 2.540 0.254 41.910 15.240 13.818 (TYP) 16.510 3.302 1.905 1.778 17.018 3.556 2.159 1.905 0.356 42.037 15.494 13.920 0.152 41.783 14.986 13.716 0.590 0.600 0.610 0.010 1.650 0.630 0.100 0.544 (TYP) 0.650 0.670 0.548 0.540 0.120 0.130 0.140 0.065 0.085 0.065 0.075 0.075 0.070
0.010 0.149 _ 0.154 Nom. _ 0.159 Max.
0.013 0.045 0.006 1.645 0.023 0.055 0.014 1.655
Copyright
2004 March Chiplus Semiconductor Corp. All rights reserved. .
Rev. 1.2 P 15

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